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SambaNova · accelerator

Verified 5mo ago

SambaNova SN40L Reconfigurable Dataflow Unit

Three-tier-memory dataflow accelerator: on-chip SRAM, HBM3, and TB-class DDR5 per socket.

Stylized line drawing of the SambaNova SN40L Reconfigurable Dataflow Unit

The SN40L is a TSMC 5nm 2.5D dataflow chip with 1,040 Pattern Compute Units delivering 638 BF16 TFLOPS per socket. Its three-tier memory hierarchy — 520 MB SRAM, 64 GB HBM3, and 1.5 TB DDR5 — targets trillion-parameter MoE serving.

Specs

compute
SambaNova RDU (TSMC 5nm)

Reconfigurable dataflow accelerator with a three-tier memory hierarchy. Targets MoE serving where DDR-tier capacity matters.

No longer SambaNova's newest chip: on 2026-02-24 it introduced the fifth-generation SN50 RDU, due to ship to customers later in 2026, alongside a planned multi-year collaboration with Intel. SambaNova's RDU page now leads with the SN50 and still lists the SN40 family.