Three-tier-memory dataflow accelerator: on-chip SRAM, HBM3, and TB-class DDR5 per socket.
The SN40L is a TSMC 5nm 2.5D dataflow chip with 1,040 Pattern Compute Units delivering 638 BF16 TFLOPS per socket. Its three-tier memory hierarchy — 520 MB SRAM, 64 GB HBM3, and 1.5 TB DDR5 — targets trillion-parameter MoE serving.
Specs
compute
SambaNova RDU (TSMC 5nm)
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