Category · Accelerator

CDNA 3 OAM accelerator with HBM3 and TSMC 5nm/6nm chiplets.

2026-05-01 · verified 2026-05-01

CDNA 3 refresh: HBM3E in the same OAM envelope as MI300X.

2026-05-01 · verified 2026-05-01

CDNA 4 OAM: HBM3E, native FP4/FP6, liquid-cooled flagship.

2026-05-01 · verified 2026-05-01

Wafer-scale AI engine: trillions of transistors and hundreds of thousands of cores on a single TSMC 5nm die.

2026-05-01 · verified 2026-05-01

Inference-only ASIC trading HBM for on-die SRAM — deterministic latency for LLM serving.

2026-05-01 · verified 2026-05-01

OAM accelerator with HBM2E and on-die RoCE Ethernet for scale-out without external NICs.

2026-05-01 · verified 2026-05-01

Blackwell SXM module designed as a drop-in for HGX H100 baseboards. Lower-TDP sibling of B200.

2026-05-01 · verified 2026-05-01

Blackwell SXM module. Dual-die GPU with HBM3e, fifth-gen NVLink. Building block of HGX B200, DGX B200, and GB200.

2026-05-01 · verified 2026-05-01

One Grace CPU coherently linked to two Blackwell GPUs over NVLink-C2C. Unit cell of the NVL72.

2026-05-01 · verified 2026-05-01

Grace Arm CPU and Hopper GPU on one module, joined by NVLink-C2C, with HBM3e on the GPU side.

2026-05-01 · verified 2026-05-01

Hopper-generation SXM accelerator: HBM3, fourth-gen Tensor Cores, the workhorse of the LLM training era.

2026-05-01 · verified 2026-05-01

Hopper-generation SXM accelerator with HBM3e, drop-in for HGX H100 baseboards.

2026-05-01 · verified 2026-05-01

Eight-GPU Blackwell baseboard. HBM3e, NVLink 5 fabric, foundation of OEM Blackwell servers.

2026-05-01 · verified 2026-05-01

Three-tier-memory dataflow accelerator: on-chip SRAM, HBM3, and TB-class DDR5 per socket.

2026-05-01 · verified 2026-05-01